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Some Arm targets such as Cortex-A9 might lack of integer division instructions, and the current shecc would not generate the correct instruction sequence for them. Consequently, we have to provide the fallback by means of software emulation. Here is the reference implementation for integer division:
__div:
push {fp, lr}
addfp, sp, #4// check for divide by zerocmpr1, #0beq__div_endpush {r0, r1}
// variablesmovr0, #0// quotientpop {r1, r2} // dividend / remainder, divisormovr3, #1// bit field__div_shift:
// shift divisor left until it exceeds dividend// the bit field will be shifted by one lesscmpr2, r1lsllsr2, r2, #1lsllsr3, r3, #1bls__div_shift__div_sub:
// cmp sets the carry flag if r1 - r2 is positive, which is weirdcmpr1, r2// subtract divisor from the remainder if it was smaller// this also sets the carry flag since the result is positivesubcsr1, r1, r2// add bit field to the quotient if the divisor was smalleraddcsr0, r0, r3// shift bit field right, setting the carry flag if it underflowslsrsr3, r3, #1// shift divisor right if bit field has not underflowedlsrccr2, r2, #1// loop if bit field has not underflowedbcc__div_sub__div_end:
subsp, fp, #4pop {fp, pc}
jserv
changed the title
Support Arm targets without integer division instructions
Support Arm/RISC-V targets without integer division instructions
Oct 27, 2023
Some Arm targets such as Cortex-A9 might lack of integer division instructions, and the current
shecc
would not generate the correct instruction sequence for them. Consequently, we have to provide the fallback by means of software emulation. Here is the reference implementation for integer division:Reference:
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