Open-source high-performance RISC-V processor
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Updated
Jun 13, 2024 - Scala
Open-source high-performance RISC-V processor
Framework that integrates the serverless benchmark suite vSwarm with gem5, the state-of-the-art research platform for system-and microarchitecture.
A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program.
high instruction-level-parallelism (ILP) using Resource-Flow-Execution
A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
High performance Bitcoin development platform
Simple TLB (Translation lookaside buffer) realization on verilog.
Achieve peak performance on x86 CPUs and NVIDIA GPUs
program execution simulator on processors
⏰ Computer Architecture and Security Conference Deadline Countdowns (Based on AI Deadlines)
A cross platform C99 library to get cpu features at runtime.
My notes from the computer science course at The University of Manchester.
Learning the x86-64 microarchitecture by analyzing data measured using assembly language.
Microarchitectural exploitation and other hardware attacks.
Kite: Architecture Simulator for RISC-V Instruction Set
A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
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