sdram
Here are 40 public repositories matching this topic...
Simple SDRAM controller written in SystemVerilog
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Jun 1, 2022 - SystemVerilog
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
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Jul 8, 2021 - Verilog
Projects using the Sipeed Tang Primer FPGA development board
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Dec 6, 2020 - Verilog
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
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Oct 15, 2023 - Verilog
(LGPL) Demonstration of how to use a memory-mapped SDRAM through the Flexible Memory Controller
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Jul 30, 2017 - C
🛠 A SDRAM controller in Verilog HDL
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Mar 21, 2022 - Verilog
Basic implementation of SDRAM controller for De0-nano board.
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Jun 2, 2024 - Verilog
High-Speed SystemVerilog SDRAM Controller
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Jan 27, 2024 - SystemVerilog
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Aug 9, 2018 - Verilog
An initial project for STM32F429ZI (aka STM32F429I-Disco1). It uses LL but no HAL.
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Oct 22, 2020 - C
SDR SDRAM Controller with Avalon-MM bus; [Bugged, deprecated]
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Apr 11, 2022 - Verilog
SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
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Jul 1, 2022 - HTML
SDRAM Tester implemented in FPGA
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May 1, 2021 - VHDL
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