sdram
Here are 40 public repositories matching this topic...
(LGPL) Demonstration of how to use a memory-mapped SDRAM through the Flexible Memory Controller
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Jul 30, 2017 - C
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
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Oct 30, 2017 - Verilog
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Aug 9, 2018 - Verilog
Simple SDRAM Controller for DE10-Lite.
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Jan 20, 2019 - Verilog
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
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Sep 7, 2020 - Verilog
An initial project for STM32F429ZI (aka STM32F429I-Disco1). It uses LL but no HAL.
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Oct 22, 2020 - C
Projects using the Sipeed Tang Primer FPGA development board
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Dec 6, 2020 - Verilog
This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz.
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Feb 7, 2021 - Verilog
simple sdram controller
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Feb 9, 2021 - Verilog
SDRAM Tester implemented in FPGA
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May 1, 2021 - VHDL
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
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Jul 8, 2021 - Verilog
SDRAM controller optimized to a memory bandwidth of 316MB/s
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Aug 16, 2021 - Verilog
Harsh Environment CubeSat Payload designed to evaluate three different manufacturing nodes SDR SDRAM technologies under space radiation conditions. It was developed for the FloripaSat-2 CubeSat mission.
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Sep 7, 2021 - VHDL
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