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Evaluation of timing performance of deep neural networks workloads accelerated on Versal AI Engine in presence of contention on shared resources, mainly caused by ARM Cortex A72 dual-core microprocessor.
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Nov 6, 2023 - Jupyter Notebook
Template for using Xilinx Vivado and SDK with CMPE-661 (HWSW Crypto) projects in a version control friendly way.
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Jun 12, 2023 - VHDL
C library for shared memory and messaging using inter processor interrupts.
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May 7, 2023 - C
Design and Analysis of an FPGA-based Wallace Multiplier.
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Jan 20, 2024 - Jupyter Notebook
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
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Mar 6, 2024 - C
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Feb 12, 2018
A microprocessor implemented in VHDL
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Feb 4, 2017 - C++
Keep Xilinx Vivado projects as minimal git repositories. A fork of https://github.com/Digilent/digilent-vivado-scripts
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Nov 23, 2021 - Tcl
Develop an 8-bit ALU on XILINX FPGA, capable of executing 16 diverse operations. Introduction: An ALU is a crucial part of CPUs, performing arithmetic and logic tasks on instruction operands. This project aims to create an efficient ALU with a focus on both arithmetic and logic functionalities.
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Aug 28, 2023 - C
Docker container containing the Vitis 2023.2 tools & PetaLinux
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Apr 8, 2024 - Dockerfile
Tutorial and base project: TEE on AMD Zynq UltraScale+ using Arm TrustZone
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Apr 10, 2024 - C
Team John Cena's Entry for the 2017 PYNQ Hackathon
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Oct 9, 2017 - Jupyter Notebook
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