Peripheral access precautions for correct memory ordering

[xipengwang]

@liuyanqi We probably need to address this issue sometime later.
Apparently, I forgot it when I wrote i2c.

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The BCM2835 system uses an AMBA AXI-compatible interface structure. In order to keep
the system complexity low and data throughput high, the BCM2835 AXI system does not
always return read data in-order 2 . The GPU has special logic to cope with data arriving out-
of-order; however the ARM core does not contain such logic. Therefore some precautions
must be taken when using the ARM to access peripherals.
Accesses to the same peripheral will always arrive and return in-order. It is only when
switching from one peripheral to another that data can arrive out-of-order. The simplest way
to make sure that data is processed in-order is to place a memory barrier instruction at critical
positions in the code. You should place:

• A memory write barrier before the first write to a peripheral.
• A memory read barrier after the last read of a peripheral.

It is not required to put a memory barrier instruction after each read or write access. Only at
those places in the code where it is possible that a peripheral read or write may be followed
by a read or write of a different peripheral. This is normally at the entry and exit points of the
peripheral service code.
As interrupts can appear anywhere in the code so you should safeguard those. If an interrupt
routine reads from a peripheral the routine should start with a memory read barrier. If an
interrupt routine writes to a peripheral the routine should end with a memory write barrier.