Pinned

1. riscv-3-stage-pipelined-processor-core riscv-3-stage-pipelined-processor-core Public

   Fully implemented 3 staged pipelined RISC-V processor with hazard detection unit. Hazard detection unit solves the hazards by stalling and forwarding technique. CSR and MRET Instructions are also s…

   SystemVerilog 1

2. duty-cycle-and-frequency-controlled-signal-using-verilog duty-cycle-and-frequency-controlled-signal-using-verilog Public

   We will make a signal in Verilog which will be a variable duty cycle as well as variable frequency signal which is named as pulse. We can refer this signal pulse as a square wave also with variable…

   Verilog 1

3. spi-protocol spi-protocol Public

   SPI protocol is implemented and simulated successfully in this repository.

   Verilog

4. uart-application-in-real-time-simulation-emulation-on-fpga uart-application-in-real-time-simulation-emulation-on-fpga Public

   If we run out of input pins on FPGA, we can instantiate receiver of uart in DUT (design under test). Receiver will receive data from PC serially and convert this serial data to parallel data and gi…

   HTML

5. pak-dsp pak-dsp Public

   Application class Digital Signal Processor that can be used in Signal Conditioning and Image Processing applications.

   SystemVerilog 1