AArch64: Separate fmls vector subtraction into vector elements #6519
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ryanmkurtz
added
Feature: Processor/AARCH64
Status: Triage
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As part of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed an unexpected behaviour in the fmls instruction for AARCH64. According to Section C7.2.126, the expected behaviour is to operate on several items stored within a single reigster. While the current behaviour instead treats the entire vector register as a single value.
e.g.:
53cfae0e"fmls v19.2S, v26.2S, v14.2S" with z19=0xbff34c546c04b2a7, z26=0xc37b69b4ba630f35, z14=0xbeb4b66dc01ec6fbHardware Reference: 0xc2b546ac6c04b2a7
Existing Spec: 0xc2b1797b3b0cd514
Patched Spec: 0xc2b546ac6c04b2a7