AArch32: vsel "gt" condition missing NG & OV flag equality check #6531
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* added 'and N == V' check missed in the vselcond "gt"
ryanmkurtz
added
Feature: Processor/ARM
Status: Triage
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As part of a research project testing the accuracy of the SLEIGH specifications compared to real hardware, we observed an unexpected behaviour in the
vselgtinstruction for both, AArch32 (ARM:LE:32:v8) & Thumb (ARM:LE:32:v8T).According to the manual, it is a floating-point conditional select that makes the destination register to take the value in either one or the other source register according to the "gt" condition. However, we noticed the output was incorrect.
This patch is similar to an already existing constructor in the x86 SLEIGH specification as shown here.
e.g, for AArch32 with,
Instruction:
0xa17a7afe, vselgt.f32 s15,s21,s3initial_registers:
{ "q0": 0x8448927d97a680d18cd6b3dbe2314e37, "q5": 0x9979037dd3f2dc8f07906f37e010f2bd, "q3": 0x24c8d61cd2a6426faae5e54bb2c1a276, "NG": 0x1, "ZR": 0x0, "OV": 0x0 }We get:
Hardware:
{ "q3": 0x8448927dd2a6426faae5e54bb2c1a276 }Patched Spec:
{ "q3": 0x8448927dd2a6426faae5e54bb2c1a276 }Existing Spec:
{ "q3": 0x7906f37d2a6426faae5e54bb2c1a276 }e.g, for Thumb with,
Instruction:
0x73fea4aa, vselgt.f32 s21,s7,s9initial_registers:
{ "q1": 0x7b287a26dcdce5c5a50d617a7c19e34a, "q2": 0x3f6e38d7a2297057bdaefa5c13765026, "q5": 0xa711bccf5300d256e55923cb9d75e855, "NG": 0x1, "ZR": 0x0, "OV": 0x0 }We get:
Hardware:
{ "q5": 0xa711bccf5300d256bdaefa5c9d75e855 }Patched Spec:
{ "q5": 0xa711bccf5300d256bdaefa5c9d75e855 }Existing Spec:
{ "q5": 0xa711bccf5300d2567b287a269d75e855 }Note: The patched spec does not introduce any disassembly changes to the best of our knowledge.