AArch32: vmvn had incorrect double-word order and number of bytes provided instead of bits in bitwise left shift

[Sleigh-InSPECtor]

As part of a research project testing the accuracy of the SLEIGH specifications compared to real hardware, we observed an unexpected behaviour in the vmvn instruction for both, AArch32 (ARM:LE:32:v8) & Thumb (ARM:LE:32:v8T).

According to the manual, it takes a value from a register, inverts the value of each bit, and places the result in the destination register. However, we noticed the output was incorrect.

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e.g, for AArch32 with,

Instruction: 0xe005f0f3, vmvn q8,q8
initial_registers: { "q8": 0xffffffffffffffff }

We get:

Hardware: { "q8": 0xffffffffffffffff0000000000000000 }
Patched Spec: { "q8": 0xffffffffffffffff0000000000000000 }
Existing Spec: { "q8": 0xffffffffffffffff }

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e.g, for Thumb with,

Instruction: 0xf0ffe005, vmvn q8,q8
initial_registers: { "q8": 0x0 }

We get:

Hardware: { "q8": 0xffffffffffffffffffffffffffffffff }
Patched Spec: { "q8": 0xffffffffffffffffffffffffffffffff }
Existing Spec: { "q8": 0xffffffffffffffffff }

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Note: The patched spec does not introduce any disassembly changes to the best of our knowledge.