You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog
Unleash the power of VLSI design! From logic gates conception through integrated circuit creation to meticulous layout design, sculpt the heart of electronic systems. Dive into a world where every nanometer matters. 🚀🔧 #VLSI #ICDesign
This repository is about design and implementation of a time interleaved SAR ADC in Cadence Virtuoso. In this project all the blocks of the ADC is customised and implemented from transistor level itself and no ideal block is used from the libraries of virtuoso.
This is a 4-bit pipelined carry-ripple adder. The design has been optimized for delay. To view the project, download the zip file and open the project in Cadence Virtuoso.