A seamless python to Cadence Virtuoso Skill interface
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Updated
Apr 24, 2024 - Python
A seamless python to Cadence Virtuoso Skill interface
Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)
Designed and simulated an inverter in Cadence
This repository contains a simple approach to design single stage operational amplifier using gpdk180 in Cadence Virtuoso.
This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
Unleash the power of VLSI design! From logic gates conception through integrated circuit creation to meticulous layout design, sculpt the heart of electronic systems. Dive into a world where every nanometer matters. 🚀🔧 #VLSI #ICDesign
Software and documentation views in Cadence Virtuoso
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Power / (fs*2ENOB).
Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.
Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Implementation of a MIPS CPU using Verilog.
Some codes I have implemented during my 10 day Training under VLSI DOMAIN
Cadence Virtuoso Design Management System
This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…
A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence
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